Make-Up List Updated

Students with red background is added to the make-up list. The make-ups will be performed with REGULAR MORNING SCHEDULE, STARTING 9:00. Be ready on time.

17.06.2008

Importing Xilinx projects to another computer

While importing your projects to another computer, you should use the import project feature of the Xilinx. Simply copying the project folder to another computer would not work. You may use builtin help of the Xilinx program if you need futher information of import function.

11.06.2008

Make-Up List

The make-ups will be performed on Wednesday, 18th of June. The final student list going to take make-ups is given below.

09.06.2008

Laboratory is Available for Projects

The laboratory will be available for projects. You can work in the Lab with Xilinx cards during this week in working hours.

09.06.2008

Project List Updated

Project lists are updated. Note that there may be demo hour changes (not day) even if you have not requested a reschedule. This list is final and there will be no further update on demo schedule.

01.06.2008

About Projects

During development of your projects, you can use basic logic gates, multiplexers, decoders, encoders and flip-flops directly from library. In addition to these, you can also use binary to seven segment converters which you may need during implementation. If you need any other combinational or sequential circuits, you should build them by using above mentioned blocks.

25.05.2008

About Finals

You can find a guide about finals here.

24.05.2008

Make-Up Dates

The make-ups will be performed on Wednesday, 18th of June. The students who will take make-ups, must e-mail to Alperen Toprak [toprakmems.eee.metu.edu.tr], no later than June 1st. Indicate your excuses for taking make-up and the experiment that you need to recover.

23.05.2008

Project Demonstrations

The project demonstration schedule is announced in here. Please read the instructions given with schedule carefully and be ready at your demo time. Failing to do so will result in your project would not be evaluated. If you need to change your demo date and time, find a group with same project and same demo assistant that is willing to exchange demo-times with you and e-mail to Ata Tuna CIFTLIK (ciftlikmetu.edu.tr) no later than June 1st.

There are two hours given for each group, one indicating your demo hour, and the one indicating availability of the laboratory to your group. Come to lab at the given time. Coming earlier would not be useful as there is no table that you can work on. If you come later, there is not enough time to set up your circuit. There are more than one and a half hour period to set up your circuit.

Be ready at your demo hour, in the specified room, and specified table, with your circuit ready to work, and your printed, complete project report. There will be names (A,B) on the room doors and numbers (1,2 ..) on the tables for project demos. Your assistant will be ready at your table, at the time assigned. If you are not there, you cannot present your project anymore. You have total of 40 minutes to represent your work, 15 minutes for each student alone and 10 minutes of circuit demonstration. After your demo, you have 20 minutes to leave your table as it is appointed to another group.

Project reports should be given at the demo time. The reports should be a formal design report with introduction, body and conclustions, and include detailed design progress together with the proper references to the material you have used as source.

Unfortunately, during demo dates, lab will not be available to other students. Only the appointed students will be allowed to get in at the specified coming hour.

23.05.2008

Attention to Monday Afternoon Group

Your laboratory session that has been missed due to May 19th holiday will be performed on May 24th Saturday. Be ready in laboratory at 13:40 on that date.

20.05.2008

About Project Demonstrations

The project demonstrations will be held on June 13-16. A detailed project demonstration schedule will be annoced soon. Please check website regularly.

20.05.2008

About Finals

The practical final exams will be carried out next week (May 26-30). Each student will attend the final on his/her own laboratory session. There will be two exam groups for each session. The following tables show the start times of the finals:

The laboratory partners will attend the exam at different sessions. One whose surname comes first in the alphabetical order will enter the first final exam group. Those who want to switch their final exam sessions with their partnets due to obligations should mail to Ata Tuna CIFTLIK (ciftlikmetu.edu.tr) until May 24th.

If you have a medical report for the day of your final exam, you should inform assistants as soon as possible. Except some extreme cases, there will not be any make-ups for the finals, and each student must attend in his/her own laboratory session.

20.05.2008

Sample Verilog Tutorial

You can download sample verilog tutorial here.

09.05.2008

Verilog Tutorial Schedule

Verilog Tutorials will be held at room D131 on Thursday 10.40 and Friday 16.40. Both of these sessions cover the same topic. Please attend one of these tutorial sessions. Note that sessions last less than one hour.

06.05.2008

Verilog Tutorial

This week, there will be a verilog tutorial on Thursday and Friday, and attendance to one of these tutorials is mandatory. In experiment 6, there will be quiz questions about verilog language. The exact hours are not determined yet but check the webpage on monday.

04.05.2008

Project Preliminary Reports

The submission date of project preliminary reports are postponed to 5th of May, Monday, at 11:30 am. If you do not bring your preliminary report till this deadline, you will get "0" as the project grade.

01.05.2008

Welcome to EE314 Laboratory

Welcome to EE314 laboratory where you will learn a lot. The laboratory works will start in the 10-14 March week. All the announcements about this course will be on this page. So we strongly advice you to follow this page regularly.

Since an important amount of you will work on circuit design after graduation, these laboratories are great chance for you to increase your skills. So try to learn as much as possible. There will be a challenging project at the end of the semester. You are expected to design a complete system. You will learn a lot while working on your projects.

As you know from EE313, preliminary works are very important to increase your performance. Do spend time on preliminary works. If your assistant thinks that your work is not enough, (s)he may not allow you to attend the laboratory.

There will be no report collected at the end of the laboratory. This has one advantage and one disadvantage. You will not have to write down everything and will not waste time. However, since there is no report, your assistant should grade your performance during the laboratory. So, the questions your assistant asked during laboratory are very important.

Similar to EE313, there will be a simple quiz before the lab. You should correctly answer 2 of 4 multiple-choice questions. Otherwise, your grade from that experiment will be divided by 2.

04.03.2008

Lab Sessions

Verilog Tutorial

Old Announcements